Charge pump voltage generators are widely used for powering certain electronic circuits at a specified boosted voltage VOut (higher than the supply voltage) that must remain substantially constant notwithstanding variations of the current absorbed by the load currently connected to the output of the boosted voltage generator. Keeping the output boosted voltage VOut of a charge pump substantially constant for ensuring the correct operation of the powered electronic circuits may be difficult in certain situations.
As depicted in FIG. 1A, in a nonvolatile memory device, the output node of the boosted voltage generator may be connected through an array of switches Si (i=1 . . . N) HV MANAGEMENT to respective loads Li, and switching from a load to another may cause an abrupt variation of the current drawn from the charge pump. To better understand how this may happen reference is made to FIG. 1b that shows a charge pump powering a load. The load is illustrated as a current generator drawing a current IL from the charge pump, in parallel with a capacitor CL representing the capacitance of the load. If at the instant of connecting the load to the output of the charge pump, the capacitance CL of the load is already charged at the nominal output voltage generated by the charge pump, only the current IL will be absorbed by the load. By contrast, if at the instant of connecting the load to the output of the charge pump the capacitance CL is practically discharged, a current sensibly greater than IL will charge the load capacitance.
Especially in memory devices, charge-pump generators must power loads of relatively large capacitance. If for example the load capacitance is practically discharged when a certain load is switched to the output node of the powering boosted voltage generator, the charge pump circuit may be momentarily unable to provide the specified voltage, and the output voltage VOut may even drop to zero.
Problems may arise when a load is disconnected from the output node Out of the charge pump and a different load is connected thereto, as shown in FIG. 2. At the instant the new connection is made, the voltage VOut may undergo a sensible variation, either increase or decrease, before reaching the correct value (for example VX2) specified for the new load (for example L2) to be powered. These abrupt variations of the voltage VOutdo not cause problems to the integrity of the transistors of the charge pump if they are designed to withstand a comfortably higher voltage than the largest voltage that may be foreseen, in other words so-called “high-voltage” transistors, because their relatively thicker gate oxides may withstand relatively high voltage differences VOX, between gate and source, between gate and drain and between gate and body. At the same time, the channel length of these “high-voltage” transistors are such that even by applying relatively high voltage differences VDS between their drain and source, the underlying depletion regions do not merge, and therefore punch-through of the channel, which could cause extraordinarily large drain-source current likely to damage the transistor, is prevented.
However, there is a penalty in using high-voltage transistors for the charge pump circuit because of the increased silicon area required. For this reason, very often the transistors of the charge pump are “normal” low-voltage transistors, as shown in the latch charge pump circuit of FIG. 3. In this situation, the transistors of the last stage of the multistage charge pump are likely to be damaged through the breaking of their gate oxide if the applied voltage VOX becomes larger than the design supply voltage Vdd. Moreover, because the channels of normal low-voltage transistors are relatively shorter than those of high-voltage transistors, if the drain-source voltage VDS exceeds the supply voltage Vdd, the channels are likely to be punched-through and the transistors damaged.
To prevent these risks that may be determined by a large and abrupt variation of the voltage VOut, it is known to interpose two protection circuits between the output node of the charge pump and the array of switches HV MANAGEMENT, as depicted in FIG. 4. A first protection circuit, UP PROTECTION, protects the devices of the charge pump when the output voltage VOut increases while the other, DOWN PROTECTION, protects the devices of the charge pump when the voltage VOut decreases. Indeed, these dedicated protection circuits may be used to protect any charge pump. For simplicity, only the circuit DOWN PROTECTION will be analyzed in detail.
As shown in FIG. 5, the circuit DOWN PROTECTION protect the transistors of the charge pump by preventing the voltage VOut from following the voltage VOutExt when it decreases abruptly. This circuit must be effective even in the worst case, that is when the voltage VOutExt undergoes the largest possible variation. As depicted in FIG. 6, this situation takes place when a load L1 charged at the maximum boosted voltage VXMax is disconnected and a load L2 is completely connected to the output of the charge pump.
A circuit for protecting the charge pump devices acts substantially as a voltage limiter, by preventing the voltage VOutIntto decrease below a minimum value VOutmin. A voltage limiter may be realized by inserting a high-voltage PMOS between the output node of the charge pump and the switches HV MANAGEMENT, as shown in FIG. 7. The gate of the high voltage PMOS transistor is set to a reference voltage VRef such to prevent the output voltage of the charge pump VOutInt from falling below a value VOutminVOutmin=VRef+VTh  (1)VTh being the threshold voltage of the PMOS transistor.
Preferably, the voltage VOutmin is close to the maximum admissible boosted voltage VXMax on a load, for limiting as much as possible the range of the output voltage VOutExt within which it may vary without turning off the PMOS. A limit condition is:VOutmin=VXMax  (2)In so doing the voltage VOutInt remains constantVOutInt=VOutmin=VXMax  (3)and the charge pump is protected.
Unfortunately, a constant voltage VOutInt implies that the current IOut delivered by the charge pump be constant and this is a drawback both in transient as well as in steady state conditions. To better understand why this is a drawback, consider first the case of steady state functioning and model the loads Li to be powered by the charge pump with current generators ILi. For dimensioning the charge pump it is necessary to determine its total capacitance CTot, given by the following equation:
                              C          Tot                =                                            N              2                                                                        (                                      N                    +                    1                                    )                                ⁢                                  V                  dd                                            -                              V                OutInt                                              ·                                    I              Out                        f                                              (        4        )            wherein f is the frequency of the clock signal used by the charged pump. To evaluate the maximum total capacitance, in the above equation (4), the current IOut is substituted with the maximum current IXMax that the loads Li may absorb, while the voltage VOutInt is the maximum possible voltage VXMax. The maximum capacitance CTotLim is
                              C          TotLim                =                                            N              2                                                                        (                                      N                    +                    1                                    )                                ⁢                                  V                  dd                                            -                              V                XMax                                              ⁢                                    I              XMax                        f                                              (        5        )            The voltage on the load is always smaller than or equal to the voltage VXMax. 
If the voltage on the load is VXMax, then the voltage limiter does not introduce any loss of efficiency, while if it is smaller than VXMax, the voltage limiter causes inefficiency by not allowing the voltage VOutInt to become smaller than the voltage VXMax. By contrast, without the limiter, the voltage VOutInt would decrease to a desired voltage VXDes and this would allow the charge pump to deliver to the load a current IXDes larger than the maximum current that it may deliver in presence of the voltage limiter. This situation is illustrated by the diagram of FIG. 8.
Alternatively, a charge pump without voltage limiter for delivering a certain maximum current IXMax, at a certain voltage VXDes<VXMax, could be designed with a smaller capacitance than that CTotLim required when the voltage limiter is present. Therefore, the presence of the voltage limiter in steady state conditions implies increasing the design capacitance CTot of the charge pump and thus the silicon area requisite.
The graph of FIG. 9 is a sample voltage-capacitance characteristic of a charge pump for a certain current IOut. The operation is analyzed in transient conditions by supposing that the charge pump must initially charge a completely discharged capacitance Ci. In a charge pump with voltage limiter, the voltage VOutInt equals VXMax, thus the delivered current and the raising slope of the voltage VOutExt are kept constant for the whole charge time, as shown by the straight line in FIG. 10. Without voltage limiter, the output voltage of the charge pump in transient conditions rise quickly from 0 to VXMax and the charge pump is able to provide a larger current than with the voltage limiter, thus achieving a charge time trNoLim smaller than trLim or, for the same charge time trLim, it requires a reduced silicon area.
By summarizing, the drawback of using the voltage limiter is that of fixing the voltage VOutmim. If VOutmin is smaller than VXMax the charge pump may be damaged. If VOutmin equals VXMax the charge pump is protected but the silicon area occupied by the charge pump is increased.
To avoid the drawbacks determined by the presence of a voltage limiter, it is necessary to use a circuit capable of varying the voltage VOutInt, in particular a circuit capable of reducing it from its maximum value (for instance VXMax) to zero, for adapting it as necessary. This circuit should also let the voltage VOutInt decrease slowly in respect to a clock period for permitting the internal nodes Int of the charge pump to fall in line with the gradual voltage reduction.
Referring to FIG. 11, a charge pump is shown with its parasitic output node capacitance COutInt powering a generic load Li initially at null voltage. The voltage VOutInt may undergo a large and abrupt reduction that could damage the transistors of the charge pump. This voltage drop is due to the large absorbed current IC and to the consequent discharge of the capacitance COutInt. To prevent any abrupt reduction of the voltage VOutInt, a current limiter is commonly used, as shown in FIG. 12. To let the voltage VOutInt decrease toward zero with a controlled slope such to prevent the risk of damaging the charge pump, the maximum current ILim allowed by the voltage limiter is properly chosen. In steady state conditions, the capacitance COutInt does not absorb any current, thusILim=IOut  (6)
The possibility of VOutInt dropping to zero must be contemplated, therefore the current ILim must be larger than or equal to the current IOut that would be obtained with a null voltage VOutInt, that is:ILim≧IOut|VOutInt=0  (7)
This is inconvenient. In fact the current IOut when VOutInt is null is two or three times larger than the current IOut when the voltage VOutInt is equal to VXMax.IOut|VOutInt=0≅2÷3IOut|VOutInt=steady—state  (8)
In turn, the current ILim must be larger than or equal to IOut|VOutInt= and this may determine an excessively fast decreasing of the voltage VOutInt. For example, for a charge pump that must provide a steady state current IOut|VOutInt=steady—state of 1 mA at a frequency f of 20 MHz, with a parasitic capacitance COutInt of 1 pF, the slope of VOutInt would be:
                                                                                          ⅆ                                      V                    OutInt                                                                    ⅆ                  t                                            =                                                                    I                    Lim                                    -                                                            I                      Out                                        ⁢                                                                                        VOutInt                        =                        steady_state                                                                                                              C                  OutInt                                                                                                        =                                                                                          (                                              1                        ÷                        2                                            )                                        ·                    1                                    ⁢                  m                  ⁢                                                                          ⁢                  A                                                  1                  ⁢                  p                  ⁢                                                                          ⁢                  F                                                                                                        =                                                1                  ÷                  2                                ⁢                                  V                                      n                    ⁢                                                                                  ⁢                    s                                                                                                          (        9        )            Therefore, in a half-period of 25 ns of the clock, the voltage VOutInt would drop by about 25-50V, and this is very risky for the charge pump integrity.
To prevent this, it is a common practice to connect a relatively large additional capacitor CAdd in parallel with the capacitance COutInt, as shown in FIG. 13, for letting the voltage VOutInt decrease to zero with a less steep slope
                                          ⅆ                          V              OutInt                                            ⅆ            t                          =                                            1              ÷              2                        ⁢                          I              Out                        ⁢                                                        VOutInt                =                steady_state                                                                        C              OutInt                        +                          C              Add                                                          (        10        )            Unfortunately, the required additional capacitor occupies a relatively large silicon area.